Putting Weak Memory in Order via a Promising Intermediate Representation

We investigate the problem of developing an "in-order" shared-memory concurrency model for languages like C and C++, which executes instructions following their program order, is thus more amenable to reasoning verification compared recent complex proposals with out-of-order execution. demonstrate that it possible fully support non-atomic accesses in in-order a way validates all compiler optimizations are performed single-threaded code (including irrelevant load introduction). The key doing so utilize distinction between source (with catch-fire semantics) intermediate representation (IR) undefined value racy reads) formally establish soundness mapping from IR. As relaxed atomic accesses, must forbid load-store reordering. discuss rather limited performance impact this fact present pragmatic approach problem, which, long term, requires new kind hardware store implementing stores. IR semantics proposed paper based on versions promising semantics, correctness proofs mappings Armv8 mechanized Coq. This work first relate goal having without any overhead non-atomics.